The present invention relates to a method for correcting crosstalk as one of layout corrections to render crosstalk between wires harmless in layout designing of a semiconductor integrated circuit.
In recent years, with the miniaturization in semiconductor manufacturing technology, crosstalk cannot be ignored. Crosstalk exerts an influence via coupling capacitance between adjacent wires by the transition of signals thereof in a semiconductor integrated circuit. This phenomenon causes delay variation, timing limitation infringement, or the function error that logic is inverted.
Accordingly, in the layout design of a semiconductor integrated circuit, there has been needed crosstalk correction for correcting the layout in order not to cause the timing limitation infringement or logic inversion due to crosstalk as well as the detection of the occurrence of crosstalk.
In a conventional method for correcting crosstalk, a repeater buffer is inserted into a net affected by the occurrence of crosstalk, and the wiring thereof is divided to reduce the coupling capacitance between the wires, thereby suppressing crosstalk (referred to as buffer insertion, for example, refer to patent literature 1).
In addition, there is provided shield wiring fixed to a constant voltage at one or both sides of wiring affected by the occurrence of crosstalk to reduce the coupling capacitance with affecting wiring (referred to as shielding).
Furthermore, in some cases, the following methods have been used: the current driving capability of a cell which drives a net affected by crosstalk is increased to hardly exert a crosstalk influence by the transition of signals in adjacent wires (referred to as cell sizing) or wiring is detoured to avoid an occurrence position of crosstalk (referred to as wiring detour, refer to non-patent literature 1).    (Patent Literature 1)    Japanese Patent Laid-Open Publication No. 3175653    (Non-Patent Literature 1)    Synopsys, Inc., “AstroPrimer Introduction to Astro Timing Optimized Layout Release 2001.2), users manual, U.S., SynopsysCorporation, February 2001, pages 13 to 20
However, the above-mentioned conventional methods for preventing crosstalk have problems that layout resources are consumed for the insertion of buffers or shield wiring, or the upgrade of the cell, that the area is increased, or that an increase in the capacitance and the use of a cell with large current driving capability lead to increased power consumption. Furthermore, as for the wiring detour, new coupling capacitance with another wiring is generated in the detour to thereby cause new crosstalk, which deteriorates the convergence of timing design.